An integrated circuit (IC) die may include electrical devices that are integrated with a semiconductor substrate. The IC die may also include conductive paths that electrically couple the electrical devices to one another and to external connections. The die may include several layers of conductive paths, with each layer separated from adjacent layers by an inter-layer dielectric (ILD). The ILD may comprise material having an extremely low dielectric constant (k) in order to minimize capacitance coupling and crosstalk between the conductive paths.
Low-k ILD materials often exhibit a coefficient of thermal expansion (CTE) that differs from other elements to which they are coupled, such as the other elements of the IC die and elements of an IC substrate to which the IC die is coupled. Moreover, low-k ILD materials are often brittle. These two characteristics may cause low-k ILD materials to crack during IC die fabrication and/or IC package to IC die assembly.
A power source such as a voltage regulator may provide power signals to an IC substrate/die package during operation. When the IC die transitions from a relatively idle state to a relatively active state, the resulting demand on the power source typically causes the power signals to exhibit a “first droop”. The magnitude of the first droop may be decreased by adding capacitance to the power delivery system. According to some approaches, capacitance is added by mounting chip capacitors on a die side and/or a land side of the IC substrate. Using these approaches, it can be difficult and/or inefficient to provide an amount of capacitance that will sufficiently decrease the magnitude of the first droop while keeping the inductance of the power delivery system low enough to result in a desired IC package performance.